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HD74SSTV32852
24-bit to 48-bit Registered Buffer with SSTL_2 Inputs and Outputs
REJ03D0833-0400 (Previous: ADE-205-687C) Rev.4.00 Apr 07, 2006
Description
The HD74SSTV32852 is a 24-bit to 48-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input. Data flow from D to QA, QB is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins. When RESET is low, all registers are reset and all outputs are low. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
Features
* * * * Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input ) Differential SSTL_2 (Stub series terminated logic) CLK signal Pinout optimizes DIMM PCB layout Ordering Information
Part Name HD74SSTV32852LBEL Package Type LFBGA-114pin Package Code (Previous code) PLBG0114GA-A (BP-114V) LB Package Abbreviation Taping Abbreviation (Quantity) EL (1,000 pcs / Reel)
Function Table
Inputs RESET *2 L H H CLK CLK LK L X or floating CLK X or floating D X or floating H L QA L H L
*1
Outputs QB L H L Q0
*1
H L or H H or L X Q0 H: High level L: Low level X: Immaterial : Low to high transition : High to low transition Notes: 1. Output level before the indicated steady state input conditions were established. 2. See under the figure.
Rev.4.00 Apr 07, 2006 page 1 of 8
HD74SSTV32852
Pin Arrangement
1 A Height 1.4 mm 0.8 mm pitch 0.5 mm 114-Ball B C D E F G H J K L M N P R T U V W
16 mm
5.5 mm
2
3
4
5
6
(Top view)
Terminal Assignment
A B C D E F G H J K L M N P R T U V W 1 Q2A Q3A Q5A Q7A Q8A Q10A Q12A Q13A Q14A Q17A Q18A Q20A Q22A Q23A Q24A D2 D4 D5 D8 2 Q1A VDDQ Q4A Q6A GND Q9A Q11A VCC Q15A Q16A Q19A VDDQ Q21A VDDQ VCC D1 D3 D7 D9 3 CLK GND VDDQ GND VDDQ VDDQ GND VDDQ GND VDDQ GND GND VDDQ GND RESET D6 D10 D11 D12 4 CLK GND VDDQ GND VDDQ VDDQ GND VDDQ GND VDDQ GND GND VDDQ GND VREF D18 D22 D23 D24 5 Q1B VDDQ Q4B Q6B GND Q9B Q11B VCC Q15B Q16B Q19B VDDQ Q21B VDDQ VCC D13 D15 D19 D21 6 Q2B Q3B Q5B Q7B Q8B Q10B Q12B Q13B Q14B Q17B Q18B Q20B Q22B Q23B Q24B D14 D16 D17 D20
Rev.4.00 Apr 07, 2006 page 2 of 8
HD74SSTV32852
Absolute Maximum Ratings
Item Supply voltage Input voltage *1 Output voltage *1 Input clamp current Output clamp current Continuous output current VCC, VDDQ or GND current / pin Package thermal impedance Storage temperature Notes: Symbol VCC or VDDQ VI VO IIK IOK IO ICC, IDDQ or IGND JA Tstg Ratings -0.5 to 3.6 -0.5 to VDDQ+0.5 -0.5 to VDDQ+0.5 50 50 50 100 36 -65 to +150 Unit V V V mA mA mA mA C/W C Conditions
VI < 0 or VI > VCC VO < 0 or VO > VDDQ VO = 0 to VDDQ
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Recommended Operating Conditions
Item Supply voltage Output supply voltage Reference voltage Termination voltage Input voltage AC high level input voltage AC low level input voltage DC high level input voltage DC low level input voltage High level input voltage Low level input voltage Differential (Common mode range) input voltage (Minimum peak to peak input) High level output current Low level output current Operating temperature Symbol VCC VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VCMR VPP IOH IOL Ta Min VDDQ 2.3 1.15 VREF-40 mV 0 VREF+310 mV -- VREF+150 mV -- 1.7 -0.3 0.97 360 -- -- 0 Typ 2.5 2.5 1.25 VREF -- -- -- -- -- -- -- -- -- -- -- -- Max 2.7 2.7 1.35 VREF+40 mV VCC -- VREF-310 mV -- VREF-150 mV VDDQ+0.3 0.7 1.53 -- -20 20 70 Unit V V V V V V V V V V V V mV mA mA C Conditions
VREF = 0.5 x VDDQ
D D D D RESET RESET CLK, CLK CLK, CLK
Note: The RESET input of the device must be held at VDDQ or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is low.
Rev.4.00 Apr 07, 2006 page 3 of 8
HD74SSTV32852
Logic Diagram
*1
RESET CLK CLK D1
R3 A3 A4 T2
1D C1
R4
A2 A5
Q1A Q1B
VREF
R
To 23 other channels
Note:
1. RESET input gate is connected to VDDQ.
Electrical Characteristics
Item Input diode voltage Output voltage Symbol VIK VOH VOL Input current (All inputs) Quiescent supply current Standby current Dynamic operating clock only IIN ICC
*2
VCC (V) 2.3
Min --
Typ -- -- -- -- -- -- -- -- 80
Max -1.2 -- VDDQ 0.2 0.35 5 35 10 --
Unit V V
Test Conditions IIN = -18 mA IOH = -100 A IOH = -16 mA IOL = 100 A IOL = 16 mA VIN = 2.7 V or 0 VIN = VIH(AC) or VIL(AC), IO = 0 RESET = GND RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50%
2.3 to 2.7 VCC-0.2 2.3 1.95 2.3 to 2.7 -- 2.3 0 2.7 -- 2.7 -- 2.7 2.7 -- --
A mA A A/ clock MHz A/ clock MHz/ data input pF
ICC (stdy) ICCD *2
duty cycle Dynamic operating per each data input ICCD
*2
2.7
--
14
--
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle.
Output high *3 Output low *3 rOH - rOL each separate bit Data inputs Input capacitance CLK and CLK RESET
*3
rOH rOL rO() CIN
2.3 to 2.7 2.3 to 2.7 2.5 2.5 *1
7 7 -- 4.0 3.0 3.5
-- -- -- -- -- --
20 20 4 5.0 4.0 5.0
IOH = -20 mA IOL = 20 mA IO = 20 mA, Ta = 25C VI = VREF310 mV
VCMR = 1.25 V, VPP = 360 mV
VI = VCC or GND
Notes: 1. All typical values are at VCC = 2.5 V, Ta = 25C. 2. Total ICC (max) = ICC + {ICCD (clock)xf(clock)} + {ICCD (Data)x1/2f(clock)x24} 3. This is effective in the case that it did terminate by resistance.
Rev.4.00 Apr 07, 2006 page 4 of 8
HD74SSTV32852
Switching Characteristics
Item Clock frequency *1 Setup time Fast slew rate *4, 6 Slow slew rate *5, 6 Hold time Fast slew rate *4, 6 Slow slew rate *5, 6 Differential inputs active time Differential inputs inactive time Symbol fclock tsu th tact tinact VCC = 2.5 0.2 V Min Max -- 200 0.75 -- 0.9 -- 0.75 -- 0.9 -- 22 -- 22 -- Unit MHz ns ns ns ns Test Condition Data before CLK, CLK Data after CLK, CLK Data inputs must be low after RESET high. Data and clock inputs must be held at valid levels (not floating) after RESET low. CLK, CLK "H" or "L"
Pulse width Output slew *3
tw tSL
2.5 1
-- 4
ns volt/ns
(CL = 30 pF, RL = 50 , VREF = VTT = VDDQ x 0.5)
Item Maximum clock frequency Propagation delay time Notes: 1. 2. 3. 4. 5. 6.
*2
Symbol fmax
VCC = 2.5 0.2 V Min 200 Typ -- Max --
Unit MHz
FROM (Input)
TO (Output)
tPLH, tPHL 1.1 -- 3.1 ns CLK, CLK QA, QB tPHL -- -- 5.0 RESET QA, QB Although the clock is differential, all timing is relative to CLK going high and CLK going low. lative This timing relationship is specified into test load (see waveforms - 3, 4) with all of the outputs switching. Assumes into an equivalent, distributed load to the address net structure defined in the application def information provided in this specification. For data signal input slew rate 1 V/ns. For data signal input slew rate 0.5 V/ns and < 1 V/ns. CLK, CLK signals input slew rates are 1 V/ns.
Rev.4.00 Apr 07, 2006 page 5 of 8
HD74SSTV32852
Test Circuit
VTT
*2
50 Test point
*1
C L = 30 pF
Notes:
1. CL includes probe and jig capacitance. 2. VTT = VREF = VDDQ x 0.5
Waveforms - 1
LVCMOS RESET Input VCC VCC /2 tinact
*1
VCC /2 0V tact 90 % 10 % I CCH I CCL
I CC
Waveforms - 2
tw VIH Input VREF VREF VIL
Timing input
VCMR
VPP
tsu
th VIH
Input
VREF
VREF VIL
Rev.4.00 Apr 07, 2006 page 6 of 8
HD74SSTV32852 Waveforms - 3
Timing input VCMR VCMR VPP
tPLH
tPHL V OH
Output
VTT
VTT VOL
Waveforms - 4
LVCMOS RESET Input VIH VCC /2 VIL tPHL VOH Output VTT VOL
Notes:
1. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. 2. All input pulses are supplied by generators having the following characteristics : PRR 10 MHz, Zo = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). , 3. The outputs are measured one at a time with one transition per measurement. 4. VTT = VREF = VDDQ/2 5. VIH = VREF+310 mV (AC voltage levels) for differential inputs. VIH = VCC for LVCMOS input. 6. VIL = VREF-310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 7. tPLH and tPHL are the same as tpd
Rev.4.00 Apr 07, 2006 page 7 of 8
HD74SSTV32852
Package Dimensions
JEITA Package Code P-LFBGA114-5.5x16-0.80 RENESAS Code PLBG0114GA-A Previous Code BP-114/BP-114V MASS[Typ.] 0.22g
wSA
D
wSB
Pin#1 Index
x4
v y1 S
S
A
y
S A
e
ZD
W V U T R P N M L K J H G F E D
e
A1
E
Reference Symbol
Dimension in Millimeters
Min
Nom 5.50 16.00
Max
D E
B
v w A A1 e b x 0.40 0.35 0.40 0.80 0.50
0.15 0.20 1.40 0.45 0.60 0.08 0.10 0.2
ZE
C B A
y y1 SD
INDEX MARK
1
2
3
4
5
6
SE
b
xM S A B
ZD ZE
0.75 0.80
Rev.4.00 Apr 07, 2006 page 8 of 8
Sales Strategic Planning Div.
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